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Ordering number : ENN4363D
LC6527N/F/L, 6528N/F/L
CMOS IC
LC6527N/F/L, 6528N/F/L
Single Chip 4-Bit Microcontroller for Small-Scale Control-Oriented Applications
The LC6527N / F / L, LC6528N / F / L belong to our single-chip 4-bit microcontroller LC6500 series fabicated using CMOS process technology and are suited for use in small-scale control-oriented applications. Their basic asrchitecture and instruction set are the same. Application areas include the standard logic circuits and applications where the number of controls is small. The LC6527N / F / L, LC6528N / F / L have relation to the LC6527C / H, LC6528C / H. The C version can be replaced by N version, and the H version (a part of the function is different). The L version is added as a low voltage version. The following show the careful difference of C and N version when you replace C version with N version. C version N version Operating Temperature -30C to +70C -40C to +85C 1-pin C oscillation exist not exist 400kHz MURATA C1=C2=330pF C1=C2=220pF R=0 R=2.2k 800kHz MURATA C1=C2=220pF C1=C2=100pF R=0 R=2.2k KYOCERA C1=C2=220pF C1=C2=110pF R=0 1MHz MURATA C1=C2=220pF C1=C2=100pF R=0 R=2.2k (Note) The suffix of recommend oscillation is changed C version and N version, but the characteristic is no change.
Features
1) CMOS technology for a low-power operation (with instruction-controlled standby function) 2) ROM / RAM LC6527N / F / L ROM : 1K ! 8bits, RAM : 64 ! 4bits LC6528N / F / L ROM : 0.5K ! 8bits, RAM : 32 ! 4bits 3) Instruction set : 51 kinds selectable from 80 instructions common to the LC6500 series 4) Wide operating voltage range from 2.2V to 6.0V (L version) 5) Instruction cycle time of 0.92s (F version)
Any and all SANYO products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft's control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. Consult with your SANYO representative nearest you before using any SANYO products described or contained herein in such applications. SANYO assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO products described or contained herein.
CF Oscillation Constant
SANYO Electric Co.,Ltd. Semiconductor Company
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
Ver. 1.01A 72294 13001 RM (IM) YATSU No.4363-1/28
LC6527N/F/L, 6528N/F/L
6) Flexible I / O port * Number of ports : 4 ports / 13 pins max. * All ports : Input / output common Input / output voltage 15V max. (open drain type) Output current 20mA max. (sink current) (LED direct drivable) * Option selectable for your intended system A. Open drain output, pull-up resistor : Single-bit select for all ports B. Output level at the reset mode : 4-bit select of H / L level for port C / D 7) Stack level : 4 levels 8) Timer : 4-bit prescaler+8-bit programmable timer 9) Clock oscillation option selectable for your intended system * Oscillator option :2-pin RC oscillation (N, L version) 2-pin ceramic resonator oscillation, 1-pin external clock input (N, F, L version) * Predivider option : No predivider, 1 / 3 predivider, 1 / 4 predivider (N, L version)
Function Table
Item Memory ROM RAM Instruction set LC6527N / 28N 1024 ! 8 bits (27N) 512 ! 8 bits (28N) 64 ! 4 bits (27N) 32 ! 4 bits (28N) 51 LC6527F / 28F 1024 ! 8 bits (27F) 512 ! 8 bits (28F) 64 ! 4 bits (27F) 32 ! 4 bits (28F) 51 LC6527L / 28L 1024 ! 8 bits (27L) 512 ! 8 bits (28L) 64 ! 4 bits (27L) 32 ! 4 bits (28L) 51
Instruction Oscillation Characteristic Input / output port On-chip function
4-bit prescaler+8-bit timer 4-bit prescaler+8-bit timer 4-bit prescaler+8-bit timer 4 4 4 Standby available Standby available Standby available by HALT instruction by HALT instruction by HALT instruction Number of ports I / O 13 max. I / O 13 max. I / O 13 max. I / O voltage 15V max. 15V max. 15V max. Output current 10mA typ. 20mA max. 10mA typ. 20mA max. 10mA typ. 20mA max. I / O circuit configuration Open drain (N-channel) or pull-up resistor-provided output selectable bit by bit. Output level at reset mode "H" or "L" level selectable port by port (port C, D only) Minimum cycle time 2.77s (VDD4V) 0.92s (VDD4.5V) 3.84s (VDD2.2V) 6.0s (VDD3V) Supply voltage 3 to 6V 4.5 to 6V 2.2 to 6V Current dissipation 2.5mA typ. 4mA typ. 2.5mA typ. Resonator RC (850kHz, 400kHz typ.) RC (400kHz typ.) ceramic (400k, 800k,1MHz, ceramic 4MHz ceramic (400k, 800k,1MHz, 4MHz) 4MHz) predivider option 1 / 1, 1 / 3, 1 / 4 1/1 1 / 1, 1 / 3, 1 / 4 Other Package DIP18, MFP18* DIP18, MFP18* DIP18, MFP18* (Note) Information on the resonator and oscillation circuit constants will be presented as soon as the recommended circuit is determined. *MFP18 : under development
Timer Stack level Standby function
No.4363-2/28
LC6527N/F/L, 6528N/F/L Pin Assignment
LC6527N / F / L LC6528N / F / L
OSC1 TEST VSS RES PA0 PA1 PA2 PA3 VDD 1 2 3 4 5 6 7 8 9 18 17 16 15 14 13 12 11 10 OSC2 / PH0 PD3
Package Dimentions
unit : mm 3007B
24.0
18
10
7.62 6.4
PD1 PD0 PC3 PC2 PC1 PC0 (1.84)
1
9
3.85max (3.25)
2.54
0.5
1.2
SANYO : DIP18(300mil)
ILC00139
Common to DIP * MFP unit : mm 3095 * Do not immerse the package in the solder dip tank when mounting the MFP on the substrate.
18 10
0.51min
12.6
0.35
1.27
1.22
SANYO : MFP-18(300mil)
(Note) The package is the reference figure without the description of the rank. Please inquire us for the formal package.
0.1 1.5
0.625
1
9
1.8max
0.15
6.35 7.6
5.4
3.3
No.4363-3/28
0.25
PD2
LC6527N/F/L, 6528N/F/L Pin Name
OSC1, OSC2 : R, C or ceramic resonator for OSC RES : Reset PA 0-3 : Input / output common port A 0-3 PC 0-3 : Input / output common port C 0-3 PD 0-3 : Input / output common port D 0-3 PH0 : Input / output common port H 0 TEST : Test
System Block Diagram
LC6527N / F / L, LC6528N / F / L
PA0-3
PC0-3
PD0-3
PH0
OSC2 Note 1
OSC1
Note 1 OSC TEST RES VDD VSS
Port A
Port C
Port D
Port H
I / O BUS RAM (Note 2) PC STACK1 STACK2 STACK3 I / O Buffer DP STACK4 I.R I.DEC ROM (Note 2)
SYSTEM BUS
E
A
ALU CF
STS ZF TMF
TM
ILC00140
Note1. The PH0 pin or OSC2 pin is selected by the mask option. Note2. LC6527N / F / N ROM : 1024 bytes RAM : 64 words LC6528N / F / N ROM : 512 bytes RAM : 32 words
No.4363-4/28
LC6527N/F/L, 6528N/F/L Development Support Tools
The following are available to support the program development for the LC6527, LC6528. (1) User's Manual "LC6527, LC6528 User's Manual" No. 24-6016 ('86.10.1.) Note : Do not use "LC6523 Series User's Manual" No.16A-7015 and No.16-9064. (2) Development Tool Manual For the EVA-800 or the EVA-850 system, refer to "EVA-800. LC6527, LC6528 Development Tool Manual". (3) Development Tools A. For program evaluation 1. Piggy back (LC65PG23 / 26) 2. 23T27 ; The pin-to-pin conversion socket for the piggy back LC65PG23 / 26. B. EVA-86000 system for program development is on development. C. For program evaluation microcontroller built-in EPROM (LC65E29)+conversion substrate (29T027)
Note. For notes for program evaluation, do not fail to refer to `4-3. Notes when evaluating programs'in "LC6527, LC6528 User's Manual".
to EVA-410 or EVA-420
EPROM (2732, 2764)
EPROM LC6596
CN-1 FAP-40-03#2
FAP-20-03#2 CN-3 FAS-20-03B
NFP-30A-0112 (34A) CN2
Piggy back LC65PG23 / 26
45cm
2.54mm pitch flat cable 1 pin 2.54mm pitch DIP18
Conversion board 23T27
FGP-20-01#2 removed the10 pin and 11 pin can be used for the DIP18.
ILC00141
ILC00142
Fig.1 Evaluation kit terget board (EVA-TB6523C / 26C / 27C / 28C)
Fig. 2 Program evaluation
No.4363-5/28
LC6527N/F/L, 6528N/F/L
D. For program development (EVA-800 or EVA-850 system) 1. MS-DOS for host system (Note 1) 2. Cross assembler......MS-DOS base cross assembler : 3. Host control program 4. Evaluation chip : LC6596 5. Emulator : EVA-800 or EVA-850 emulator and evaluation boards EVA800-TB6527 / 28
Appearance of Development Support System
* Host processor control program * LC65S.EXE cross assembler
MS--DOS personal computer
EVA-800 or EVA-850 emulator (note 2)
CN1, CN2
LC6596 CN3 CABLE9 Evaluation chip board EVA800-TB6527 / 28
FS-20 SAP20 1 pin User's application board Remove the 10 and 11 pin, and use for DIP18
ILC00143
(Note 1) MS-DOS : Trademark of Microsoft Corporation (Note 2) The EVA-800, EVA-850 are general term for emulator. A suffix (A, B,...) is added at the end of EVA-800 and EVA-850 as they are improved to be a newer version. Do not use the EVA-800 and EVA-850 with no suffix added.
No.4363-6/28
LC6527N/F/L, 6528N/F/L Pin Description
Pin name Pins I / O Function VDD 1 - Power supply VSS 1 - OSC1 1 Input * Pin for externally connecting RC, ceramic resonator for system clock generation. * For 1-pin external clock input, the PH0 / OSC2 pin is used as I / O port PH0. * For 2-pin RC OSC, 2-pin ceramic resonator OSC, the PH0 / OSC2 pin is used as OSC pin OSC2. PA 0 to 4 Input / * I / O port A0 to 3 PA3 output 4-bit input (IP instruction) 4-bit output (OP instruction) Single-bit decision (BP, BNP instruction) Single-bit set / reset (SPB, RPB instruction) * Standby is controlled by PA3. * The PA3 pin must be free from chattering during the HALT instruction execution cycle. PC0 to 4 Input / * I / O port C0 to 3 PC3 output same as for PA0 to 3 (Note) * Option permits output at the reset mode to be "H" or "L". (Note) No standby control function is provided. Option - 1) 1-pin external clock input 2) 2-pin RC OSC 3) 2-pin ceramic resonator OSC 4) Predivider option 1. No predivider 2. 1 / 3 predivider 3. 1 / 4 predivider 1) Open drain type output 2) With pull-up resistor 1), 2) : Specified bit by bit Reset Mode - -
* "H" output (Output Nch transistor : OFF)
1) Open drain type output
PD0 to PD3 PH0 / OSC2
RES
TEST
4 Input / * I / O port D0 to 3 output Same as for PC0 to 3 1 Input / * I / O port H0 Same as for PA0 to 3 output Same as for PA0 to 3 (Note) * Single-bit configuration * For 2-pin OSC, this pin is used as the OSC2 pin, providing no function as I / O port. (Note) No standby control function is provided 1 Input * System reset input * For power-up reset, C is connected externally. * For reset restart, "L" level is applied for 4 clock cycles or more. 1 Input * LSI test pin Normally connected to VSS
2) With pull-up resistor 3) Output at reset mode : "H" 4) Output at reset mode : "L" * 1), 2) : Specified bit by bit * 3), 4) : Specified in a group of 4 bits Same as for PC0 to 3 Same as for PC0 to 3 Same as for PA0 to 3
* "H" output * "L" output (Option-selectable)
No.4363-7/28
LC6527N/F/L, 6528N/F/L Oscillator circuit option
Option Name 1. External clock Circuit
OSC1
ILC00102
Conditions, etc. The PH0 / OSC2 pin is used as port PH0. The PH0 / OSC2 pin is used as OSC pin OSC2, providing no function as port.
2. 2-pin RC OSC
Cext
OSC1
PH0 / OSC2 Rext
ILC00144
3. Ceramic resonator OSC
Ceramic resonator
C1
OSC1
PH0 / OSC2 R
ILC00145
The PH0 / OSC2 pin is used as OSC pin OSC2, providing no function as port.
C2
Predivider Option
Option Name 1. No predivider (1 / 1) Circuit
OSC circuit
fOSC
ILC00105
2. 1 / 3 predivider
OSC circuit
fOSC
1/3 predivider
ILC00106
3. 1 / 4 predivider
OSC circuit
Timing generator
fOSC 3
Conditions, etc. * Applicable to all of 3 OSC options. * The OSC frequency, external clock do not exceed 1444kHz. (LC6527N, 6528N) * The OSC frequency, external clock do not exceed 4330kHz. (LC6527F, 6528F) * The OSC frequency, external clock do not exceed 1040kHz. (LC6527L, 6528L) * Applicable to only 2 OSC options of external clock, ceramic resonator OSC. * The OSC frequency, external clock do not exceed 4330kHz.
Timing generator
fOSC
1/4 predivider
ILC00107
Note : The OSC option and predivider option are summarized below. Full care must be exercised.
Timing generator
fOSC 4
* Applicable to only 2 OSC options of external clock, ceramic resonator OSC. * The OSC frequency, external clock do not exceed 4330kHz.
No.4363-8/28
LC6527N/F/L, 6528N/F/L
Table of OSC, predivider Option of LC6527N / 28N, 27F / 28F and 27L / 28L LC6527N, LC6528N Circuit Configuration Frequency Predivider Option VDD Range Remarks (Cycle time) Ceramic resonator OSC 400kHz 1 / 1 (10s) 3 to 6V Unusable with 1 / 3, 1 / 4 predivider 800kHz 1 / 1 (5s) 4 to 6V 1 / 3 (15s) 4 to 6V 1 / 4 (20s) 4 to 6V 1MHz 1 / 1 (4s) 4 to 6V 1 / 3 (12s) 4 to 6V 1 / 4 (16s) 4 to 6V 4kHz 1 / 3 (3s) 4 to 6V Unusable with 1 / 1 predivider 1 / 4 (4s) 4 to 6V 1-pin external clock 200k to 677kHz 1 / 1 (20 to 6s) 3 to 6V 600k to 2000kHz 1 / 3 (20 to 6s) 3 to 6V 800k to 2667kHz 1 / 4 (20 to 6s) 3 to 6V 200k to 1444kHz 1 / 1 (20 to 2.77s) 4 to 6V 600k to 4330kHz 1 / 3 (20 to 2.77s) 4 to 6V 800k to 4330kHz 1 / 4 (20 to 3.70s) 4 to 6V External clock by 2-pin Same as above RC OSC circuit 2-pin RC Used with 1 / 1 predivider, 3 to 6V recommended constants. If used with 4 to 6V other than recommended constants, the frequency, predivider option, VDD range must be the same as for 1-pin external clock. External clock input to the The ceramic oscillation circuit cannot be driven by external clock. ceramic oscillation circuit To drive the circuit with external clock, select the external clock option or the 2-pin RC option.
LC6527F, LC6528F Circuit Configuration
Predivider Option VDD Range Remarks (Cycle time) Ceramic resonator OSC 4MHz 1 / 1 (1s) 4.5 to 6V 1-pin external clock 200k to 4330kHz 1 / 1 (20 to 0.92s) 4.5 to 6V External clock input to the The ceramic oscillation circuit cannot be driven by external clock. ceramic oscillation circuit To drive the circuit with external clock, select the external clock option.
Frequency
No.4363-9/28
LC6527N/F/L, 6528N/F/L
LC6527L, LC6528L Circuit Configuration Ceramic resonator OSC Frequency 400kHz 800kHz Predivider Option (Cycle time) 1 / 1 (10s) 1 / 1 (5s) 1 / 3 (15s) 1 / 4 (20s) 1 / 1 (4s) 1 / 3 (12s) 1 / 4 (16s) 1 / 4 (4s) 1 / 1 (20 to 3.84s) 1 / 3 (20 to 3.84s) 1 / 4 (20 to 3.84s) VDD Range 2.2 to 6V 2.2 to 6V 2.2 to 6V 2.2 to 6V 2.2 to 6V 2.2 to 6V 2.2 to 6V 2.2 to 6V 2.2 to 6V 2.2 to 6V 2.2 to 6V Remarks Unusable with 1 / 3, 1 / 4 predivider
1MHz
4kHz 1-pin external clock 200k to 1040kHz 600k to 3120kHz 800k to 4160kHz Same as above
Unusable with 1 / 1, 1 / 3 predivider
Used with 1 / 1 predivider, 2.2 to 6V recommended constants. If used with other than recommended constants, the frequency, predivider option, VDD range must be the same as for 1-pin external clock. External clock input to the The ceramic oscillation circuit cannot be driven by external clock. ceramic oscillation circuit To drive the circuit with external clock, select the external clock option or the 2-pin RC option.
External clock by 2-pin RC OSC circuit 2-pin RC
Option of ports C, D Output Level at the Reset Mode
For input / output common ports C, D either of the following two output levels may be selected in a group of 4 bits during reset by option. Option Name Conditions, etc. 1. Output at the reset mode : "H"level All of 4 bits of ports C, D 2. Output at the reset mode : "L"level All of 4 bits of ports C, D
Option of port Output Configuration
For each input / output common port, either of the following two output configurations may be selected by option. Option Name Circuit Conditions, etc. 1. Open drain output * Unapplicable to port PH0 / OSC2 when 2-pin RC OSC or ceramic resonator OSC is selected.
ILC00236
2. Output with pull-up resistor
ILC00237
No.4363-10/28
LC6527N/F/L, 6528N/F/L
LC6527N, LC6528N 1. Absolute Maximum Ratings at Ta=25C, VSS=0V Parameter Symbol Pins Maximum VDD max VDD supply voltage Output voltage VO OSC2 Input voltage Input / output voltage Peak output current Average output current VI(1) VI(2) VIO(1) VIO(2) IOP IOA IOA(1) IOA(2) Allowable power Pd max(1) dissipation Pd max(2) OSC1 (*1) TEST, RES Port of OD type Port of PU type I / O port I / O port PA0 to 3 PC0 to 3 PH0 PD0 to 3 Per pin over the period of 100ms Total current of PA0 to 3, (*2) Total current of PC0 to 3, PD0 to 3 PH0 (*2) Ta=-40 to +85C (DIP package) Ta=-40 to +85C (MFP package)*
Conditions
Limits -0.3 to +7.0V Allowable up to voltage generated -0.3 to VDD+0.3 -0.3 to VDD+0.3 -0.3 to +15 -0.3 to VDD+0.3 -2 to +20 -2 to +20 -6 to +40 -14 to +90 300 200
unit V V V V V V mA mA mA mA mW mW
-40 to +85 C Operating Topg temperature Storage Tstg -55 to +125 C temperature *******Under development. Do not immerse the package in the solder dip tank when mounting the MFP on the substrate. 2. Allowable Operating Conditions at Ta=-40C to +85C, VSS= 0V, VDD=3.0 to 6.0V Ratings Parameter Symbol Pins Conditions VDD [V] min typ Operating VDD VDD 3.0 supply voltage Standby VST VDD RAM, register hold 1.8 supply voltage (*3) "H"-level input VIH(1) Port of OD type Output Nch Tr. OFF 0.7VDD voltage (except H0) VIH(2) Port of PU type Output Nch Tr. OFF 0.7VDD (except H0) VIH(3) H0 of OD type Output Nch Tr. OFF 0.8VDD VIH(4) H0 of PU type Output Nch Tr. OFF 0.8VDD VIH(5) RES 0.8VDD VIH(6) OSC1 External clock mode 0.8VDD "L"-level input VIL(1) Port Output Nch Tr. OFF VDD=4 to 6 VSS voltage VIL(2) Port Output Nch Tr. OFF VDD=3 to 6 VSS VIL(3) OSC1 External clock mode VDD=4 to 6 VSS VIL(4) OSC1 External clock mode VDD=3 to 6 VSS VIL(5) TEST VDD=4 to 6 VSS VIL(6) TEST VDD=3 to 6 VSS VIL(7) RES VDD=4 to 6 VSS VIL(8) RES VDD=3 to 6 VSS
max 6.0 6.0 +13.5 VDD +13.5 VDD VDD VDD 0.3VDD 0.25VDD 0.25VDD 0.2VDD 0.3VDD 0.25VDD 0.25VDD 0.2VDD
unit V V V V V V V V V V V V V V V V
No.4363-11/28
LC6527N/F/L, 6528N/F/L
Parameter Operating frequency (cycle time) Symbol fop (Tcyc) Pins Conditions When the 1 / 3 or 1 / 4 predivider option is selected, clock must not exceed 4.33MHz. VDD [V] VDD=4 to 6 min 200 (20) 200 (20) Ratings typ max 1444 (2.77) 667 (6.0) unit kHz (s) kHz (s)
External clock conditions Frequency Pulse width Rise / Fall time
text
OSC1
textH, textL OSC1 textR, textF OSC1
Fig.1. When clock exceeds VDD=4 to 6 1.444MHz, the 1 / 3 3 to 6 or 1 / 4 predivider VDD=4 to 6 option is selected. 3 to 6 VDD=4 to 6 3 to 6
200 200 69 180
4330 2667
50 100
kHz kHz ns ns ns ns
Oscillation guaranty constants 2-pin RC Cext oscillation Cext Rext Rext Ceramic resonator OSC
OSC1, OSC2 OSC1, OSC2 OSC1, OSC2 OSC1, OSC2
Fig.2 Fig.2 Fig.2 Fig.2 Fig.3
VDD=3 to 6 VDD=4 to 6 VDD=3 to 6 VDD=4 to 6
2205% 2205% 121% 4.71% Table 1
pF pF k k
3. Electrical Characteristics at Ta=-40C to +85C, VSS= 0V, VDD=3.0V to 6.0V Parameter "H"-level input current Symbol IIH(1) Pins Conditions min Ratings typ max +5.0 unit A
IIH(2) "L"-level input current IIL(1) IIL(2) IIL(3) IIL(4) "H"-level output VOH(1) voltage VOH(2) "L"-level output VOL(1) voltage VOL(2) Hysteresis voltage VHIS
Port of OD type Output Nch Tr. OFF (including OFF leak current of Nch Tr.) VIN=13.5V OSC1 External clock mode, VIN=VDD Port of OD type Output Nch Tr. OFF -1.0 VIN=VSS Port of PU type Output Nch Tr. OFF -1.3 -0.35 VIN=VSS RES VIN=VSS -45 -10 OSC1 External clock mode, -1.0 VIN=VSS Port of PU type IOH=-50A VDD-1.2 VDD=4.0V to 6.0V Port of PU type IOH=-10A VDD-0.5 Port IOL=10mA VDD=4.0V to 6.0V Port IOL=1.8mA, IOL of each port : 1mA or less RES, OSC1 of 0.1VDD schmitt type(*4)
+1.0
A A mA A A V V V V V
1.5 0.4
No.4363-12/28
LC6527N/F/L, 6528N/F/L
Parameter Current dissipation 2-pin RC oscillation Symbol Pins Conditions Output Nch Tr. OFF at operating, Port=VDD IDDOP(1) IDDOP(2) IDDOP(3) IDDOP(4) IDDOP(5) IDDOP(6) IDDOP(7) VDD VDD VDD VDD VDD VDD VDD Fig.2 fosc=850kHz (TYP) VDD=4 to 6V Fig.2 fosc=400kHz (TYP) Fig.3 4MHz, 1 / 3 predivider VDD=4 to 6V Fig.3 4MHz, 1 / 4 predivider VDD=4 to 6V Fig.3 400kHz Fig.3 800kHz VDD=4 to 6V 200kHz to 667kHz, 1 / 1 predivider 600kHz to 2000kHz, 1 / 3 predivider 800kHz to 2667kHz, 1 / 4 predivider 200kHz to 1444kHz, 1 / 1 predivider 600kHz to 4330kHz, 1 / 3 predivider 800kHz to 4330kHz, 1 / 4 predivider VDD=4 to 6V Output Nch Tr. OFF VDD=6V Port=VDD VDD=3V 1.5 1.0 2.0 2.0 0.5 1.5 1.5 4 4 5 4 2 4 4 mA mA mA mA mA mA mA min Ratings typ max unit
Ceramic resonator oscillation
External clock
IDDOP(8)
VDD
2.0
5
mA
Standby mode Oscillation characteristics Ceramic OSC Frequency
IDDst
VDD VDD
0.05 0.025
10 5
A A
fCFOSC (*5)
OSC1, OSC2 OSC1, OSC2 OSC1, OSC2 OSC1, OSC2
Stable time
tCFS
2-pin RC oscillation Frequency
fMOSC
OSC1, OSC2
OSC1, OSC2
Fig.3 fo=400kHz Fig.3 fo=800kHz, VDD=4 to 6V Fig.3 fo=1MHz, VDD=4 to 6V Fig.3 fo=4MHz, 1 / 3 predivider 1 / 4 predivider, VDD=4 to 6V Fig.4 fo=400kHz Fig.4 fo=800kHz, 1MHz, 4MHz, 1 / 3 predivider, 1 / 4 predivider VDD=4 to 6V Fig.2 Cext=220pF5% Fig.2 Rext=4.7k1% VDD=4 to 6V Fig.2 Cext=220pF5% Fig.2 Rext=12k1% VDD=3 to 6V
384 768 960 3840
400 800 1000 4000
416 832 1040 4160 10 10
kHz kHz kHz kHz ms ms
646
850
1117
kHz
304
400
580
kHz
No.4363-13/28
LC6527N/F/L, 6528N/F/L
Ratings typ
Parameter
Symbol
Pins
Conditions
min
max
unit
Pull-up resistance I / O port pull-up RPP resistance External reset characteristics Reset time tRST Pin capacitance Cp
Port of PU type
VDD=5V
14
k
See Fig.5 f=1MHz Other than pins to be tested, VIN=VSS 10 pF
(*1) When oscillated internally under the oscillating conditions in Fig.3, up to the oscillation amplitude generated is allowable. (*2) Average over the period of 100ms. (*3) Operating supply voltage VDD must be held until the standby mode is entered after the execution of the HALT instruction. The PA3 pin must be free from chattering during the HALT instruction execution cycle. (*4) The OSC1 pin can be schmitt-triggered when the 2-pin RC oscillation option or external clock oscillation option has been selected. (*5) fCFOSC : oscillation frequency. There is a tolerance of approximately 1% between the center frequency at the ceramic resonator mode and the nominal value presented by the ceramic resonator supplier. For details, refer to the specification for the ceramic resonator.
No.4363-14/28
LC6527N/F/L, 6528N/F/L
OSC1
(OSC2)
External clock
OPEN
VDD 0.8VDD
0.2VDD(VDD=3-4V) 0.25VDD(VDD=4-6V) VSS textF textL textR textH
text
Fig. 1 External Clock Input Waveform
ILC00146
*External clock can be used at selecting 2-pin RC option or 1-pin external clock option, and cannot be used at ceramic resonator oscillation.
OSC1
OSC2
OSC1
OSC2
Rext Cext C1
Ceramic resonator
C2
Fig. 2 2-pin RC Oscillation Circuit
ILC00088
Fig. 3 Ceramic Resonator Oscillation Circuit
ILC00147
VDD Lower limit of operating VDD
0V OSC
Unstabilized OSC period tCFS
Stabilized OSC
Fig. 4 Oscillation Stabilizing Period
ILC00148
No.4363-15/28
LC6527N/F/L, 6528N/F/L
Table 1 Constants Guaranteed for Ceramic Resonator OSC 4MHz (Murata) C1 33pF10% CSA4.00MG C2 33pF10% CST4.00MGW (built-in C) R 0 4MHz (Kyocera) C1 33pF10% KBR4.0MSA C2 33pF10% KBR4.0MKS (built-in C) R 0 1MHz (Murata) C1 100pF10% CSB1000J C2 100pF10% R 2.2 1MHz (Kyocera) C1 100pF10% KBR1000F C2 100pF10% R 0 800kHz (Murata) C1 100pF10% CSB800J C2 100pF10% R 2.2 800kHz (Kyocera) C1 100pF10% KBR800F C2 100pF10% R 0 400kHz (Murata) C1 220pF10% CSB400P C2 220pF10% R 2.2 400kHz (Kyocera) C1 330pF10% KBR400BK C2 330pF10% R 0
RES
CRES(=0.1F)
Fig. 5 Reset Circuit
ILC00240
(Note) When the rise time of the power supply is 0, the reset time becomes 10ms to 100ms at CRES=0.1F. If the rise time of the power supply is long, the value of CRES must be increased so that the reset time becomes 10ms or more.
No.4363-16/28
LC6527N/F/L, 6528N/F/L
RC Oscillation Characteristics of the LC6527N, LC6528N Fig. 6 shows the RC oscillation characteristics of the LC6527N, LC6528N. For the variation range of RC OSC frequency of the LC6527N, LC6528N, the following are guaranteed at the external constants only shown below. 1) VDD=3.0V to 6.0V, Ta=-40C to +85C External constants Cext=220pF Rext=12k 304kHzfMOSC580kHz 2) VDD=4.0V to 6.0V, Ta=-40C to +85C Cext=220pF Rext=4.7k 646kHzfMOSC1117kHz
If any other constants than specified above are used, the range of Rext=3k to 20k, Cext=150pF to 390pF must be observed. (See Fig.6.)
(*6) : The oscillation frequency at VDD=5.0V, Ta=+25C must be in the range of 350kHz to 750kHz. (*7) : The oscillation frequency at VDD=4.0V to 6.0V, Ta=-40C to +85C and VDD=3.0V to 6.0V, Ta=-40C to 85C must be within the operation clock frequency range.
f MOSC-Rext
1.5
f MOSC[kHz]
1000 9 8 7 6 5 4 3
These characteristic curves are given for reference only without guarantee.
C=
C=
C= 39 0p
15
F
27
0p
F
0p
F
2
100 2
VDD=5(V) Ta=25(C)
3 4 5 10 2 3 4 5 100
Rext [k]
ILC00149
Fig. 6 RC Oscillation Frequency Data (Typ.)
No.4363-17/28
LC6527N/F/L, 6528N/F/L
LC6527F, LC6528F 1. Absolute Maximum Ratings at Ta=25C, VSS=0V Parameter Symbol Pins Maximum VDD max VDD supply voltage Output voltage VO OSC2 Input voltage Output voltage Peak output current Average output current VI(1) VI(2) VIO(1) VIO(2) IOP IOA IOA(1) IOA(2) Allowable power Pd max(1) dissipation Pd max(2) OSC1 (*1) TEST, RES Port of OD type Port of PU type I / O port I / O port PA0 to 3 PC0 to 3 PH0 PD0 to 3 Per pin over the period of 100ms Total current of PA0 to 3, (*2) Total current of PC0 to 3, PD0 to 3, PH0 (*2) Ta=-40 to +85C (DIP package) Ta=-40 to +85C (MFP package)*
Conditions
Limits -0.3 to +7.0V Allowable up to voltage ganerated -0.3 to VDD+0.3 -0.3 to VDD+0.3 -0.3 to +15 -0.3 to VDD+0.3 -2 to +20 -2 to +20 -6 to +40 -14 to +90 300 200
unit V V V V V V mA mA mA mA mW mW
-40 to +85 C Operating Topg temperature Storage Tstg -55 to +125 C temperature *******Under development. Do not immerse the package in the solder dip tank when mounting the MFP on the substrate. 2. Allowable Operating Conditions at Ta=-40C to +85C, VSS= 0V, VDD=4.5 to 6.0V Ratings unit Parameter Symbol Pins Conditions min typ max Operating VDD VDD 4.5 6.0 V supply voltage Standby VST VDD RAM, register hold (*3) 1.8 6.0 V supply voltage "H"-level input VIH(1) Port of OD type Output Nch Tr. OFF 0.7VDD +13.5 V voltage (except H0) VIH(2) Port of PU type Output Nch Tr. OFF 0.7VDD VDD V (except H0) VIH(3) H0 of OD type Output Nch Tr. OFF 0.8VDD +13.5 V VIH(4) H0 of PU type Output Nch Tr. OFF 0.8VDD VDD V VIH(5) RES 0.8VDD VDD V VIH(6) OSC1 External clock mode 0.8VDD VDD V "L"-level input VIL(1) Port Output Nch Tr. OFF VSS 0.3VDD V voltage VIL(2) OSC1 External clock mode VSS 0.25VDD V VIL(3) TEST VSS 0.3VDD V VIL(4) RES VSS 0.25VDD V
No.4363-18/28
LC6527N/F/L, 6528N/F/L
Parameter Operating frequency (Cycle time) External clock conditions Frequency Pulse width Rise / Fall time Oscillation guaranteed constants ceramic resonator OSC Symbol fop (Tcyc) Pins Conditions min 200 (20) Ratings typ max 4330 (0.92) unit kHz (s)
text OSC1 textH, textL OSC1 textR, textF OSC1
Fig.1
200 69
4330 50
kHz ns ns
Fig.2
See Table 1
3. Electrical Characteristics at Ta=-40C to +85C, VSS= 0V, VDD=4.5V to 6.0V Parameter "H"-level input current Symbol IIH(1) Pins Conditions min Ratings typ max +5.0 unit A
IIH(2) "L"-level input current IIL(1) IIL(2) IIL(3) IIL(4) "H"-level output voltage "L"-level output voltage Hysteresis voltage VOH(1) VOH(2) VOL(1) VOL(2) VHIS
Port of OD type Output Nch Tr. OFF (including OFF leak current of Nch Tr.) VIN=13.5V OSC1 External clock mode, VIN=VDD Port of OD type Output Nch Tr. OFF -1.0 VIN=VSS Port of PU type Output Nch Tr. OFF -1.3 -0.35 VIN=VSS RES VIN=VSS -45 -10 OSC1 External clock mode, -1.0 VIN=VSS Port of PU type IOH=-50A VDD-1.2 Port of PU type IOH=-10A VDD-0.5 Port IOL=10mA Port IOL=1.8mA, IOL of each port : 1mA or less RES, OSC1 of 0.1VDD schmitt type(*4)
+1.0
A A mA A A V V V V V
1.5 0.4
No.4363-19/28
LC6527N/F/L, 6528N/F/L
Parameter Current dissipation Ceramic resonator OSC External clock Symbol Pins Conditions min Ratings typ max unit
IDDOP(1) IDDOP(2)
VDD VDD
Fig.2 4MHz *1 200kHz to 4330kHz *1 Output Nch Tr.OFF at Operating mode Port=VDD Output Nch Tr. OFF VDD=6V Port=VDD VDD=3V
1.5 1.5
3.5 3.5
mA mA
Standby mode Oscillation characteristics Ceramic OSC Frequency Stable time Pull-up resistance I / O port pull-up resistance External reset characteristics Reset time Pin capacitance
IDDst
VDD VDD
0.05 0.025
10 5
A A
fCFOSC tCFS
OSC1, OSC2
Fig.2 fo=4MHz (*5) Fig.3 fo=4MHz
3840
4000
4160 10
kHz ms
RPP
Port of PU type
VDD=5V
14
k
tRST Cp
f=1MHz, other than pins to be tested, VIN=VSS
See Fig.4 10
pF
(*1) When oscillated internally under the oscillating conditions in Fig.2, up to the oscillation amplitude generated is allowable. (*2) Average over the period of 100ms. (*3) Operating supply voltage VDD must be held until the standby mode is entered after the execution of the HALT instruction. The PA3 pin must be free from chattering during the HALT instruction execution cycle. (*4) The OSC1 pin can be schmitt-triggered when the external clock oscillation option has been selected. (*5) fCFOSC : Oscillatable frequency.
No.4363-20/28
LC6527N/F/L, 6528N/F/L
OSC1
(OSC2)
External clock
OPEN VDD 0.8VDD
0.25VDD VSS textF textL textR textH
text
Fig. 1 External Clock Input Waveform
ILC00150
VDD Lower limit of operating VDD
0V OSC1 OSC2 OSC
C1
Ceramic resonator
C2
Unstabilized OSC period tCFS
Stabilized OSC
Fig. 2 Ceramic Resonator OSC Circuit
ILC00151
Fig. 3 OSC Stabilizing Period
ILC00152
Table 1 Constants Guaranteed for Ceramic Resonator OSC 4MHz (Murarta) C1 33pF10% CSA4.00MG C2 33pF10% CST4.00MGW (built-in C) R 0 4MHz (Kyocera) C1 33pF10% KBR4.0MSA C2 33pF10% KBR4.0MKS (built-in C) R 0
RES
CRES(=0.1F)
Fig. 4 Reset Circuit
ILC00153
(Note) When the rise time of the power supply is 0, the reset time becomes 10ms to 100ms at CRES=0.1F. If the rise time of the power supply is long, the value of CRES must be increased so that the reset time becomes 10ms or more.
No.4363-21/28
LC6527N/F/L, 6528N/F/L
LC6527L, LC6528L 1. Absolute Maximum Ratings at Ta=25C, VSS=0V Parameter Symbol Pins Maximum VDD max VDD supply voltage Output voltage VO OSC2 Input voltage Input / output voltage Peak output current Average output current VI(1) VI(2) VIO(1) VIO(2) IOP IOA IOA(1) IOA(2) Allowable power Pd max(1) dissipation Pd max(2) OSC1 (*1) TEST, RES Port of OD type Port of PU type I / O port I / O port PA0 to 3 PC0 to 3 PH0 PD0 to 3 Per pin over the period of 100ms Total current of PA0 to 3, (*2) Total current of PC0 to 3, PD0 to 3 PH0 (*2) Ta=-40 to +85C (DIP package) Ta=-40 to +85C (MFP package)*
Conditions -0.3 to +7.0
Limits
unit V V V V V V mA mA mA mA mW mW
Allowable up to votage ganerated -0.3 to VDD+0.3 -0.3 to VDD+0.3 -0.3 to +15 -0.3 to VDD+0.3 -2 to +20 -2 to +20 -6 to +40 -14 to +90 250 150
Operating Topg -40 to +85 C temperature -55 to +125 C Storage Tstg temperature *******Under development. Do not immerse the package in the solder dip tank when mounting the MFP on the substrate. 2. Allowable Operating Conditions at Ta=-40C to 85C, VSS= 0V, VDD=2.2 to 6.0V Parameter Operating supply voltage Standby supply voltage "H"-level input voltage Symbol VDD VST VIH(1) VIH(2) VIH(3) VIH(4) VIH(5) VIH(6) VIL(1) VIL(2) VIL(3) VIL(4) VDD VDD Port of OD type (except H0) Port of PU type (except H0) H0 of OD type H0 of PU type RES OSC1 Port OSC1 TEST RES RAM, register hold (*3) Output Nch Tr. OFF Output Nch Tr. OFF Output Nch Tr. OFF Output Nch Tr. OFF External clock Output Nch Tr. OFF External clock Pins Conditions min 2.2 1.8 0.7VDD 0.7VDD 0.8VDD 0.8VDD 0.8VDD 0.8VDD VSS VSS VSS VSS Ratings typ max 6.0 6.0 +13.5 VDD +13.5 VDD VDD VDD 0.2VDD 0.15VDD 0.2VDD 0.15VDD unit V V V V V V V V V V V V
"L"-level input voltage
No.4363-22/28
LC6527N/F/L, 6528N/F/L
Parameter Operating frequency (cycle time) External clock conditions Frequency Pulse width Rise / fall time Oscillation guaranteed constants 2-pin RC oscillation Ceramic oscillation Symbol fop (Tcyc) Pins Conditions When the 1 / 3 or 1 / 4 predivider option is selected, clock must not exceed 4.16MHz. min 200 (20) Ratings typ max 1040 (3.84) unit kHz (s)
text OSC1 textH, textL OSC1 textR, textF OSC1
Fig.1 When clock exceeds 1.040MHz, the 1 / 3 or 1 / 4 predivider option is selected.
200 100
4160 100
kHz ns ns
Cext Rext
OSC1, OSC2
Fig.2 Fig.3
2205% 121% See Table 1.
pF k
3. Electrical Characteristics at Ta=-40C to +85C, VSS= 0V, VDD=2.2V to 6.0V Parameter "H"-level input current Symbol IIH(1) Pins Conditions min Ratings typ max +5.0 unit A
IIH(2) "L"-level input current IIL(1) IIL(2) IIL(3) IIL(4) "H"-level output VOH voltage "L"-level output VOL(1) voltage VOL(2) Hysteresis voltage VHIS
Port of OD type Output Nch Tr. OFF (including OFF leak current of Nch Tr.) VIN=13.5V OSC1 External clock mode, VIN=VDD Port of OD type Output Nch Tr. OFF VIN=VSS Port of PU type Output Nch Tr. OFF VIN=VSS RES VIN=VSS OSC1 External clock mode, VIN=VSS Port of PU type IOH=-10A Port Port RES, OSC1 of schmitt type(*4) IOL=3mA IOL=1mA, IOL of each port : 1mA or less
+1.0 -1.0 -1.3 -45 -1.0 VDD-0.5 1.5 0.4 0.1VDD -0.35 -10
A A mA A A V V V V
No.4363-23/28
LC6527N/F/L, 6528N/F/L
Parameter Current dissipation 2-pin RC OSC Ceramic OSC Symbol Pins Conditions Output Nch Tr. OFF at operating, Port=VDD Fig.2 fOSC=400kHz (TYP) Fig.3 4MHz, 1 / 4 predivider Fig.3 4MHz, 1 / 4 predivider VDD=2.2V Fig.3 400kHz Fig.3 800kHz 200kHz to 667kHz, 1 / 1 predivider 600kHz to 2000kHz, 1 / 3 predivider 800kHz to 2667kHz, 1 / 4 predivider Output Nch Tr. OFF VDD=6V Port=VDD VDD=2.2V min Ratings typ max unit
IDDOP(1) IDDOP(2) IDDOP(3) IDDOP(4) IDDOP(5) IDDOP(6)
VDD VDD VDD VDD VDD VDD
0.8 1.2 0.5 0.5 1.0 1.0
2.5 2.5 1 2 2.5 2.5
mA mA mA mA mA mA
External clock
Standby mode Oscillation characteristics Ceramic OSC Frequency
IDDst
VDD VDD
0.05 0.025
10 5
A A
fCFOSC (*5)
OSC1, OSC2 OSC1, OSC2 OSC1, OSC2 OSC1, OSC2
Stable time
tCFS
2-pin RC OSC Frequency Pull-up resistance I / O port pull-up resistance External reset characteristics Reset time Pin capacitance
fMOSC
OSC1, OSC2
Fig.3 fo=400kHz Fig.3 fo=800kHz Fig.3 fo=1MHz Fig.3 fo=4MHz 1 / 4 predivider Fig.4 fo=400kHz Fig.4 fo=800kHz, 1MHz, 4MHz, 1 / 4 predivider Fig.2 Cext=220pF5% Fig.2 Rext=12k1%
384 768 960 3840
400 800 1000 4000
416 832 1040 4160 10 10
kHz kHz kHz kHz ms ms kHz
281
400
580
RPP
Port of PU type
VDD=5V
14
k
tRST Cp
f=1MHz Other than pins to be tested, VIN=VSS
See Fig.5. 10
pF
(*1) When oscillated internally under the oscillating conditions in Fig.3, up to the oscillation amplitude generated is allowable. (*2) Average over the period of 100ms. (*3) Operating supply voltage VDD must be held until the standby mode is entered after the execution of the HALT instruction. The PA3 pin must be free from chattering during the HALT instruction execution cycle. (*4) The OSC1 pin can be schmitt-triggered when the 2-pin RC oscillation option or external clock oscillation option has been selected. (*5) fCFOSC : Oscillatable frequency. There is a tolerance of approximately 1% between the center frequency at the ceramic resonator mode and the nominal value presented by the ceramic resonator supplier. For details, refer to the specification for the ceramic resonator.
No.4363-24/28
LC6527N/F/L, 6528N/F/L
OSC1
(OSC2)
External clock
OPEN
VDD 0.8VDD
0.15VDD VSS textF textL textR textH
text
Fig. 1 External Clock Input Waveform
ILC00154
*External clock can be used at selecting 2-pin RC option or 1-pin external clock option, and cannot be used at ceramic resonator oscillation.
OSC1
OSC2
OSC1
OSC2
Rext Cext C1
Ceramic resonator
C2
Fig. 2 2-pin RC Oscillation Circuit
ILC00088
Fig. 3 Ceramic Resonator Oscillation Circuit
ILC00147
VDD Lower limit of operating VDD
0V OSC
Stabilized OSC Unstabilized OSC period tCFS
Fig. 4 Oscillation Stabilizing Period
ILC00148
No.4363-25/28
LC6527N/F/L, 6528N/F/L
Table 1 Constants Guaranteed for Ceramic Resonator OSC 4MHz (Murata) C1 33pF10% CSA4.00MGU C2 33pF10% CST4.00MGWU (built-in C) R 0 1MHz (Murata) C1 100pF10% CSB1000J C2 100pF10% R 2.2 1MHz (Kyocera) C1 100pF10% KBR1000F C2 100pF10% R 0 800kHz (Murata) C1 100pF10% CSB800J C2 100pF10% R 2.2 800kHz (Kyocera) C1 100pF10% KBR800F C2 100pF10% R 0 400kHz (Murata) C1 220pF10% CSB400P C2 220pF10% R 2.2 400kHz (Kyocera) C1 330pF10% KBR400BK C2 330pF10% R 0
RES
CRES(=0.1F)
Fig. 5 Reset Circuit
ILC00240
(Note) When the rise time of the power supply is 0, the reset time becomes 10ms to 100ms at CRES=0.1F. If the rise time of the power supply is long, the value of CRES must be increased so that the reset time becomes 10ms or more.
No.4363-26/28
LC6527N/F/L, 6528N/F/L
RC Oscillation Characteristic of the LC6527L, LC6528L Fig. 6 shows the RC oscillation characteristic of the LC6527L, 6528L. For the variation range of RC OSC frequency of the LC6527L, 6528L, the following are guaranteed at the external constants only shown below. VDD=2.2V to 6.0V, Ta=-40C to +85C External constants Cext=220pF Rext=12k 281kHzfMOSC580kHz
If any other constants than specified above are used, the range of Rext=3k to 20k, Cext=150pF to 390pF must be observed. (See Fig.6.)
(*6) : The oscillation frequency at VDD=5.0V, Ta=+25C must be in the range of 350kHz to 500kHz. (*7) : The oscillation frequency at VDD=2.2V to 6.0V, Ta=-40C to +85C must be within the operation clock frequency range.
f MOSC-Rext
1.5
f MOSC[kHz]
1000 9 8 7 6 5 4 3
These characteristic curves are given for reference only without guarantee.
C=
C=
C= 39 0p
15
F
27
0p
F
0p
F
2
100 2
VDD=5(V) Ta=25(C)
3 4 5 10 2 3 4 5 100
Rext [k]
ILC00149
Fig. 6 RC Oscillation Frequency Data (Typ.)
No.4363-27/28
LC6527N/F/L, 6528N/F/L
Specifications of any and all SANYO products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer's products or equipment. SANYO Electric Co., Ltd. strives to supply high-quality high-reliability products. However, any and all semiconductor products fail with some probability. It is possible that these probabilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO products(including technical data,services) described or contained herein are controlled under any of applicable local export control laws and regulations, such products must not be expor ted without obtaining the expor t license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written permission of SANYO Electric Co., Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only ; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of January, 2001. Specifications and information herein are subject to change without notice.
PS No.4363-28/28

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